The inventive concept relates to a semiconductor memory device, and more particularly, to a semiconductor memory device using a full-power voltage (VDD) bit line precharge scheme using a bit line sense amplifier and a method of configuring the semiconductor memory device.
Dynamic random access memories (DRAMs), which are semiconductor memory devices, sense and amplify data stored in a memory cell by using a sense amplifier. The sense amplifier is connected to a bit line in the memory cell, and senses the data stored in the memory cell by comparing a charge sharing voltage obtained using charge sharing with the bit line with a bit line precharge voltage. The degree of accuracy of the sensed data depends on the amount of charge stored in the memory cell and the charge sharing that is affected by the capacitance of the bit line. Accordingly, a proper bit line precharge scheme is important for enhancing a data access speed of the DRAMs, and thus increase a sensing speed.
As a power voltage decreases and a voltage difference between a logic level “1” and a logic level “0” decreases, attempts have been made to develop a substitute for a conventional half VDD bit line precharge scheme. Thus, a full-VDD bit line precharge (FVBP) scheme by which a bit line is precharged to a VDD and a VSS bit line precharge scheme by which a bit line is precharged to a ground voltage (VSS) have been proposed.
However, the FVBP scheme is difficult to acceptably and stably sense data having a logic level “1” because if the data stored in the memory cell is “1”, there is no charge sharing voltage for the bit line. Also, the VSS bit line precharge scheme is difficult to acceptably and stably sense data having a logic level “0” because if the data stored in the memory cell is “0”, there is no charge sharing voltage for the bit line.
Accordingly, if a charge sharing voltage can be generated even though the data stored in the memory cell is “1”, the FVBP scheme is required to acceptably and stably sense the data at an optimal speed.